In one of my design i need to interface 2.5V I/O to 3.3V I/O.
when 3.3V device is driving signals everything is fine noise
margin for
high comes out NMh(Voh_min-Vih_min)=2.4-1.7=0.7V.
But when 2.5V device is driving signal in worst case noise margin
for high logic comes out NMh(Voh_min-Vih_min)=2.1-2.0=0.1V
which is very less and can be crossed due to signal integrity
issues.
because these signals are time critical i can add logic converter
device in between.
Is there any way i can increase noise margin for it ?
Thank You in advance
With Regards
Kapil Jain
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